What is HDL?
A Hardware Description Language (HDL) is a specialized programming language used to model digital circuits and systems. Unlike traditional programming languages such as C or Python, HDLs describe hardware behavior and structure at various levels of abstraction, including gate, register-transfer, and behavioral levels. HDLs enable designers to:
Two main HDLs dominate the industry:
Verilog HDL is widely used in designing digital circuits and systems due to its simplicity and similarity to C.
History and Evolution of Verilog
Verilog HDL was created in 1984 by Phil Moorby and Prabhu Goel at Gateway Design Automation. Initially developed as a proprietary language for simulation, Verilog evolved into a widely adopted standard for hardware design and verification.
Timeline of Key Milestones
Verilog remains a cornerstone in digital design, particularly in FPGA and ASIC development, due to its robust simulation and synthesis capabilities.
Verilog vs. VHDL: Key Differences
Verilog and VHDL are the two primary HDLs, each with unique characteristics that cater to different design needs.
| Features | Verilog | VHDL |
|---|---|---|
| Syntax | C-like Concise | Ada-like, verbose |
| Data Types | Limited,Basic Types | Strongly typed, complex |
| Design Style | Procedural & Structural | Mostly structural |
| Usage | widely in ASIC & FPGA | Common in defense & aerospace |
| Learning Curve | Easier to learn | Steeper, more rigorous |
When to Use Each Language
The choice between Verilog and VHDL often depends on project requirements, existing toolchains, and industry standards.
Applications of Verilog in FPGA and ASIC Design
Verilog HDL is pivotal in digital system design, particularly in (Field-Programmable Gate Array) and (Application-Specific Integrated Circuit) development.
Data Types and Operators
In Verilog, data types are used to define the kind of data a variable can hold. The most commonly used data types include:
reg [7:0] data; // 8-bit register-transfer
reg no; // single-bit register-transfer
wire signal; // Simple wire declaration
integer i;real float_val = 3.14;parameter WIDTH = 8;Verilog supports a wide range of operators, including:
reg [3:0] a = 4;
reg [3:0] b = 2;
reg [3:0] sum;
sum = a + b; // sum = 6
Bitwise Operators: Perform bitwise operations on vectors.
wire [3:0] c = 4'b1100;
wire [3:0] d = 4'b1010;
wire [3:0] result;
result = c & d; // result = 4'b1000
Logical Operators: Evaluate logical conditions.
cond1 = 1'b1;
wire cond2 = 1'b0;
wire logic_result;
logic_result = cond1 && cond2; // logic_result = 0
Relational Operators: Compare values.
wire is_greater = (a > b); // Evaluates to 1 if a is greater than b
Equality Operators: Compare equality.
wire is_equal = (a == b); // Checks if a is equal to b
Modules
Modules are the fundamental building blocks of a Verilog design. They define the hardware components and their behavior.
module and_gate (
input wire a,
input wire b,
output wire y
);
assign y = a & b;
endmodule
Ports
Ports serve as an interface for modules to communicate with external components.
module example_module (
input wire clk,
input wire reset,
output reg out_signal
);
Nets
Nets represent physical connections in the hardware. wire is the most common net type, which connects signals between modules.
wire internal_wire;
assign internal_wire = clk & reset;
Procedural vs. Continuous Assignments
Procedural assignments are used within always or initial blocks. They are useful for describing sequential and combinational logic.
reg [3:0] count;
always @(posedge clk or negedge reset) begin
if (!reset)
count <= 0;
else
count <= count + 1;
end
Continuous Assignments
Continuous assignments use the assign keyword for logic that is constantly evaluated.
wire sum;
assign sum = a + b; // sum updates automatically when a or b changes
Always Blocks and Sensitivity Lists
Always Block
The always block is used to model both combinational and sequential logic.
always @(posedge clk or negedge reset) begin
if (!reset)
data <= 8'b0;
else
data <= data + 1;
end
Sensitivity Lists
always @(*) begin
case (state)
2'b00: out = 1;
2'b01: out = 2;
default: out = 0;
endcase
endBlocking vs. Non-blocking Assignments
Blocking (=) AssignmentsBlocking assignments execute sequentially within a procedural block.
always @(*) begin
a = b;
c = a; // Executes only after a = b is complete
end
Non-blocking (<=) Assignments
Non-blocking assignments allow parallel execution and are crucial for flip-flop behavior in sequential logic.
always @(posedge clk) begin
a <= b;
c <= a; // Both assignments happen in parallel
end
When to Use Each
Basic Gates Implementation
Basic gates such as AND, OR, NOT, NAND, NOR, EXOR, EXNOR, BUFF, NOTIF0, NOTIF1, BUFFIF0, and BUFFIF1 are the fundamental building blocks of digital logic. These gates can be implemented in Verilog using both structural and behavioral modeling.
Examples :
1. AND Gate
module AND_Gate (input A, input B, output Y);
assign Y = A & B;
endmodule
2. OR Gate
module OR_Gate (input A, input B, output Y);
assign Y = A | B ;
endmodule
3. NOT Gatemodule NOT_Gate (input A, output Y);
assign Y = ~A;
endmodule
4. NAND Gatemodule NAND_Gate (input A, input B, output Y);
assign Y = A & B;
endmodule
5. NOR Gatemodule NOR_Gate (input A, input B, output Y);
assign Y = ~(A | B) ;
endmodule
6. EXOR Gatemodule EXOR_Gate (input A, input B, output Y);
assign Y = A ^ B ;
endmodule
7. EXNOR Gatemodule EXOR_Gate (input A, input B, output Y);
assign Y = ~(A ^ B) ;
endmodule
8. BUFF Gatemodule BUFF_Gate (input A, output Y);
assign Y = A ;
endmodule
9. NOTIF0 (Tri-State) Gate module NOTIF0 (output wire Y, input wire A, input wire E);
assign Y = (~A) & ~E ? (~A) : 1'bz;
endmodule
10. NOTIF1 (Tri-State) vate module NOTIF1 (output wire Y, input wire A, input wire E);
assign Y = (~A) & E ? (~A) : 1'bz;
endmodule