Verilog HDL Self-Learning Platform

📘 Introduction to Verilog

Verilog is a Hardware Description Language (HDL) used to model digital systems such as logic gates, processors, and memory. This platform provides a complete self-learning roadmap.

🔹 Basics

module AND_Gate(input A, input B, output Y);
  assign Y = A & B;
endmodule

▶ Run on EDA Playground

module NAND_Gate(input A, input B, output Y);
  assign Y = ~(A & B);
endmodule

module EXNOR_Gate(input A, input B, output Y);
  assign Y = ~(A ^ B);
endmodule

🔹 Combinational Logic

Examples: Multiplexers, Demultiplexers, Encoders, Decoders, Adders, Subtractors.

// 2:1 Multiplexer
module MUX2to1(input A, input B, input Sel, output Y);
  assign Y = (Sel) ? B : A;
endmodule

🔹 Sequential Logic

Examples: Latches, Flip-Flops, Counters, Shift Registers.

// D Flip-Flop
module DFF(input D, input CLK, output reg Q);
  always @(posedge CLK)
    Q <= D;
endmodule

🔹 Testbenches

module tb_AND_Gate;
  reg A, B;
  wire Y;

  AND_Gate uut(.A(A), .B(B), .Y(Y));

  initial begin
    $monitor("A=%b B=%b -> Y=%b", A, B, Y);
    A=0; B=0; #10;
    A=0; B=1; #10;
    A=1; B=0; #10;
    A=1; B=1; #10;
    $finish;
  end
endmodule

🔹 FPGA Implementation

To implement on FPGA, synthesize your Verilog code using Xilinx Vivado, Intel Quartus, or open-source Yosys.

🔹 Advanced

Topics: ALU design, Finite State Machines (FSM), Pipelining, Memory (RAM/ROM), Custom CPU design.

📝 Quizzes

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Verilog HDL